1. Field of the Invention
The present invention relates to a method of cleaning a semiconductor wafer in a semiconductor fabricating process. Especially it may be applied in the final rinse step in the semiconductor fabrication process. The present application is based on Japanese Patent application No. 2001-212204 incorporated herein by reference.
2. Description of the Related Art
In the production of semiconductor devices, a cleaning process is included between one production process and the next production process in order to remove particles (dust) and impurities adhering to the wafer surface, which exist in minute amount. Recently, as the size of semiconductor devices are becoming small, particles which are small in size or exist in low concentration are becoming a threat to the production, which raise relative importance of the cleaning technology in turn. Incidentally, the size of particles which would pose a certain problem is 0.1 μm or more, and today's control on the particle size includes particles of such sizes. If there exist a large amount of particles on a wafer, then they would cause a pattern defect, thereby reducing a manufacturing yield.
FIGS. 13A and 13B are perspective views illustrating a method for cleaning a wafer in a conventional single spin mode. As shown in FIG. 13A, a wafer 1 is held by pins 7 provided on arms 9 of a rotation apparatus 10 and rotated. An axis of rotation of the wafer 1 is perpendicular to the wafer 1 through the center of rotation 3. Since the location of the center of rotation 3 depends on how the wafer is rotated, it does not necessarily coincide with the geometric center of the wafer 1. FIGS. 14A and 14B are plan views of a rotation apparatus 10 comprising pins 7 and arms 9. FIG. 14A illustrates the rotation apparatus 10 before the wafer 1 is placed thereupon, and FIG. 14B illustrates the rotation apparatus 10 with the wafer 1 being held by the pins 7. FIG. 14C is a side view of the wafer 1 which is held by the pins 7, where the wafer 1 rotates as a whole fixture rotates around the rotational axis 8 of the rotation apparatus 10. While the wafer 1 is being rotated, deionized water (not shown in the figures) is ejected from a nozzle 2 onto the center of rotation 3, the nozzle 2 being positioned directly thereabove. Pure water is sometimes referred to as deionized water (DIW) or ultradeionized water. Therefore, it is referred to as deionized water (DIW) hereinafter. The nozzle 2 may be positioned slightly off of directly above the center of rotation 3 of the wafer 1 as illustration in FIG. 13B. In such a case, deionized water is also ejected in the direction of the center of rotation 3 from the nozzle 2. Deionized water which drops onto the center of rotation 3 on the wafer 1 moves to the periphery of the wafer 1 due to the centrifugal force generated by the rotation of the wafer 1. During that time, deionized water cleans the surface of the wafer 1. The reason that deionized water is ejected onto the center of rotation 3 is that, as described above, deionized water which drops onto the wafer 1 moves from the center of rotation 3 to the periphery of the wafer 1 and, as it so happens, the wafer 1 is efficiently cleaned with a small amount of deionized water.
Inventors of the present invention have revealed that the above-described conventional technology causes problems as described below. Specifically, when the wafer 1 is cleaned with deionized water, the destruction of thin dielectric layers, such as gate oxide films, occurs at the central portion of the wafer 1. And, materials which constitute wirings formed on the wafer 1, Cu, for example, become dissolved or oxidized at exposed portions. More detailed description will be made on a plurality of wiring patterns arranged on a wafer and covered with an insulating layer having via holes to expose the surface of the wiring pattern. If these patterns are arranged in a central portion as well as in a peripheral portion of the wafer 1, then the dissolution or oxidation of wiring metals is more likely to occur for those arranged in the central portion of the wafer 1 than for those in the peripheral portion. In particular each of the wiring patterns comprises a wiring part having a large exposed area in many via holes and a lead part having a small exposed area in a few via holes drawn from said wiring part. Incidentally, as the extent of the large exposed area is greater and that of the small exposed area is lesser, the wiring materials are more susceptible to the dissolution or oxidation. Furthermore, particles become concentrated around the central portion of the wafer, causing pattern defects.